This is binary compatible with the upcoming A15 processor, but lower speed and more power efficient. The intent is that a chip will have some A15 cores and some A7 cores and use them as appropriate to balance speed and energy consumption.

It could also be used as a standalone processor where its performance is sufficient and energy efficiency is a win.

The "Cortex A∗" numbering scheme should not be confused with the "Apple A∗" numbering scheme. They are unrelated. There is in fact an A5 in each scheme at the moment.

How much battery life is saved using an asymmetric multicore design as compared to dynamically downclocking of a "big dog" core? The article does not address this, but it does say that smaller die size of the "little dog" core uses 1/3 less power.

NVidia's Kal-El SoC implements this approach, although it uses Cortex A9 for both the Big Dog and Little Dog cores. The Little Dog is produced using low-leakage transistors, which is where their obtain their power savings (at the cost of clock speed). In the Kal-El design, the Little Dog communicates with the Big Dogs through a shared L2 cache.

Reminds me of the old BBC coprocessors, which is interesting as ARM's predecessor was Acorn Computers. Funny to see an idea from the 80's getting a second run out!

http://en.wikipedia.org/wiki/BBC_Micro_expansion_units

I doubt this will change process model or application lifecycle already present in the major smartphone OS. In the "always" on services, long-running background tasks arena the precious commodity is not cpu usually, it's memory. There is no "swap space". Interesting to see QNX\RIM listed as an early partner.

In overall power consumption how high is the CPU on the list of components? I'd imagine the display, WiFi, cell radios, Bluetooth are the real battery zappers. If a device was to be built using this big dog-little dog strategy, realistically how much battery life could expected to be gained?

iPhone 5?